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Application Note 9836
TABLE 1. HIP6020/21EVAL1 OUTPUT LOAD CAPABILITIES
NOMINAL
VOLTAGE
STATIC
TOLERANCE
DYNAMIC
TOLERANCE
NOMINAL
CURRENT
MAXIMUM
CURRENT
MAXIMUM
CURRENT
MAXIMUM
SLEW RATE
DESIGN
PLATFORM
OUTPUT
VCC_CORE
VCC_VDDQ
VCC_VDDQ
VCC_VTT
VCC_MCH
(V)
2.0
1.5/3.3
1.5/3.3
1.5
1.8
( ± ,%)
3.0
3.0
3.0
3.0
3.0
( ± ,%)
6.5
9.0
9.0
9.0
5.0
(A)
10
1.0
2.0
1.0
1.0
(A)
17.4
3.0
6.0
3.0
3.0
STEP (A)
9.5
2.0
4.0
2.0
2.0
(A/ μ s)
20.0
1.0
1.0
1.0
1.0
(EVAL1)
Both
HIP6021
HIP6020
Both
Both
When using the Intel Slot 1 EMT Tool, note that the core
regulator VID jumpers (JP0-JP4) located on the evaluation
board are in parallel with the ones located on the EMT tool.
Remember to de-populate one set of jumpers completely
and use the other set to dial-in the desired output voltage.
HIP6020/21EVAL1 Reference Designs
The evaluation board is designed to simultaneously meet all
the applicable criteria outlined in Table 1. The following
section highlights some of the most important features of this
system power solution.
ATX Power Supply Control Interface
JP7 allows control of the ATX power supply. Placing the
jumper in the 1-2 position, connects the PS-ON (output
enable) input of the ATX supply to ground, thus
unconditionally enabling the outputs. Placing the jumper in
Lossless Output Voltage Droop with Load
The synchronous switching regulator on the
HIP6020/21EVAL1 board implements output voltage droop
functions, where the output voltage sags proportionately with
the output current. Although not necessary for proper circuit
operation, this method takes advantage of the static
regulation limits to improve the dynamic regulation by
expanding the available headroom for transient edge output
excursion. In such practical applications, compared to a non-
droop implementation, this translates to fewer output
capacitors or better regulation for the same type and number
of capacitors. Figure 4 details the output voltage
characteristics of a converter with 3.0% droop compared to a
non-droop implementation.
the 2-3 position enables automatic control of the ATX. When
ATX supply turns on, the 5V stand-by output turns Q6A on to
enable the main ATX outputs. When FAULT/RT pin goes
high, Q6B latches on, thus turning off Q6A and disabling the
ATX outputs. Cycling power off and then back on re-enables
the ATX power supply. The sole purpose of this circuit is to
exemplify a possible interface between the control circuit’s
FAULT output and an ATX power supply.
2.030V
2.000V
1.970V
WITHOUT
DROOP
WITH DROOP
9
FAULT/RT
5VSB
R17
51K
0.5A OUTPUT CURRENT 17.4A
FIGURE 4. OUTPUT VOLTAGE DROOP AT 2.0V DAC SETTING
R15
5.1K
CR2
R16
5.1K
In contrast to droop implementation involving a resistive
element placed in the output current path, this method does
not involve the additional power loss introduced by the
GND
J2
14
3, 5, 7, 13
15, 16, 17
PS-ON
JP7
3
2
1
1N4148
Q6A
1/2
RF1K49154
Q6B
1/2
RF1K49154
resistor. By moving the voltage regulation point ahead of the
output inductor (at the PHASE node), droop becomes equal
to the average voltage drop across the output inductor’s DC
resistance as well as any distributed resistance. To insure
symmetric output voltage excursions in response to load
transients, the output voltage is offset above the nominal
FIGURE 3. ATX POWER SUPPLY CONTROL CIRCUIT
2
level by half the calculated droop.
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